频率范围 | 220MHz - 725MHz之间任意频率,可精确到小数点后6位 |
频率稳定性(ppm) | ±10,±20,±25,±50 |
相位抖动(ps) | 0.23ps |
输出类型 | LVPECL,LVDS,HCSL |
工作温度范围(℃) | -20 ~ +70,-40 ~ +85,-40 ~ +105 |
工作电压(V) | 2.5 ~ 3.3 |
封装尺寸(mm2) | 3.2x2.5,5.0x3.2,7.0x5.0 |
特点 | 可编程制程,任意参数自由组合 |
状态 | 量产 |
SiT9367低抖动差分晶振在实际运行条件下具有出色的动态性能
● FPGA | ● 光学模块 | ● PCIE | ● 1GB-10GB以太网 |
● SATA/SAS | ● 光纤通道 | ● 串行数据链接 | ● 系统时钟 |
● 无线和回程 |
● 测试和测量 |
● 安全设备 |
● 数据中心 |
功能引脚示意图 |
脚位 |
功能 |
|
说明 |
|
1 | OE |
Output Enable |
H[6]: specified frequency output
L: output is high impedance |
ST |
No Connect |
H or L or Open: No effect on output frequency or other device functions.
|
||
2 | NC | NA |
No Connect; Leave it floating or connect to GND for better heat dissipation |
|
3 | GND |
Power |
VDD Power Supply Ground | |
4 | OUT+ |
Output |
Oscillator output | |
5 | OUT- |
Output |
Complementary oscillator output | |
6 | VDD |
Power |
Power supply voltage[7] |
Notes:
6. In OE mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven.
7. A capacitor of value 0.1 μF or higher between VDD and GND is required. An additional 10 μF capacitor between VDD and GND is required for the best phase jitter performance.
请升级